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Showing posts with label Makefile. Show all posts
Showing posts with label Makefile. Show all posts

Thursday, 15 January 2009

Use of .PHONY targets in Makefiles, an example

Posted on 03:56 by Unknown
Targets that do not represent files are known as phony targets. Examples are standard phony targets such as "clean", "all". It also makes a target always out of date.

It is important to note that make cannot distinguish between a file target and phony target. If by chance the name of a phony target exists as a file, make will associate the file with the phony target name in its dependency graph. If, for example, the file clean happened to be created running make clean would yield the confusing message:
$ make clean
make: `clean' is up to date.

Since most phony targets do not have prerequisites, the clean target would always be considered up to date and would never execute.

To avoid this problem, GNU make includes a special target, .PHONY, to tell make that a target is not a real file. Any target can be declared phony by including it as a prerequisite of .PHONY:
.PHONY: clean
clean:
rm -f *.o

Now make will always execute the commands associated with clean even if a file named clean exists.

Here is a simple Makefile which demonstrates the problem and solution
------ Makefile --------------------------
all: print
print:
cat clean
clean:
rm *.o
--------------------------------------------
If you just call make, it outputs the contents of "clean" file present in the current working directory.
For Ex:
[siddesh@jadoo phony]$ make
cat clean
This is a clean script

Suppose if you want to run clean target to remove .o files, then you need to run "make clean". But you woudn't be getting desired output. Lets see what it reports

[siddesh@jadoo phony]$ make clean
make: `clean' is up to date.

Corrected Makefile
------------------------------------------
all: print
print:
cat clean

.PHONY: clean
clean:
rm *.o
--------------------------------------------
Now if you try "make clean", it will call clean target to clean .o files
[siddesh@jadoo phony]$ make clean
rm *.o
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Posted in Makefile | No comments

Tuesday, 1 July 2008

Automatic Variables in Makefiles

Posted on 01:36 by Unknown
Automatic variables in Makefiles (make/gmake)
$@: The filename representing the target
$%: The filename element of an archive member specification
$<: The filename of the first prerequisite
$?: The names of all prerequisite that are newer than the target, separated by spaces
$^: The filenames of all the prerequisite's, separated by spaces. (Without duplicates)
$+: Same as $^, except that it includes duplicates
$*: The stem of target filename. A stem is typically a filename without it's suffix.

User defined variables
*) A variable name can contain any characters including spaces except # and =.
*) Case sensitive
*) To get the value of a variable, enclose the variable name in $(). Single-letter variable can omit parenthesis
*) Variables can also be expanded using curly braces as in ${CC}
*) The value of a variable consists of all the words to the right of the assignment symbol with leading space trimmed. Trailing spaces are not trimmed
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Posted in Makefile | No comments
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